Embodiment generally relate to electronic circuit designs, and more specifically to improvements in architectural arrangements which enable enhanced performance and/or features for sampling receivers, and specifically to direct conversion sampling receivers which include a successive approximation analog-to-digital converter (SAR-ADC) to enhance quality of sampling receivers, where the SAR-ADC incorporates a current redistribution digital-to-analog converter (DAC) and where filtering is implemented in the radio frequency (RF) domain by at least reusing a capacitor arrays which form all or part of the DAC within the SARADC.
Direct conversion sampling receivers are a relatively new realization and are highly suited to implementation on an ultra-high speed digital process since the receiver architecture eliminates the requirement for significant analogue circuits such as operational amplifier (op-amp) based continual time filters. However, current direct conversion receivers suffer from frequency spikes caused by aliasing components which may manifest around the s3*Flo range, where a Flo is 1 GHz. This pattern will be repeated for every 2*Flo increase in frequency offset and fundamentally relates to the harmonics of the sampling clock. Such decrease in the attenuation delivered by the sampled filter characteristic will lead to an increase in aliasing components, both noise and any discrete signals folding on to the desired channel. A further problem in conventional direct conversion receivers is that the characteristic response cannot be easily modified within the present architectural arrangement therefore there is no opportunity to adaptively modify the characteristic response in dependence on received signal conditions, i.e. to maximize attenuation at a given frequency.
Therefore, there is a need in the art for an architectural arrangement which substantially overcomes the aforementioned undesired characteristics.
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